1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to a way to provide increase power line noise immunity in an integrated circuit (IC) by maximizing decoupling capacitance using a fill area.
2. Background Art
The density check is a necessary procedure after a very large scale integrated circuit (VLSI) design including layout is completed. The conventional density check process is to check local density of each material layer and determine whether the density is within the pre-determined upper and lower values. When the density is lower than the low limit, a set of small square isolated elements of the layer material are filled in the area to reach the density. These shapes are not connected to anything in the IC, so they serve no functional purpose relative to IC functioning. On the other hand, integrated circuits (ICs) require decoupling capacitors to filter out the noise generated by switching circuits. In particular, whenever a transistor switches, it generates the noise on the power line. For example, in some phase-lock-loop (PLL) systems, the digital switching noise reaches about 400 mV peak-to-peak while the power supply voltage is 1 V only. Ideally, the amount of decoupling capacitance is maximized as much as possible because the more decoupling capacitance provided, the more the noise is filtered and the noise immunity of the IC improved. However, due to the limited area available and cost of an IC, the decoupling capacitance is not able to be very large. The shapes of the decoupling capacitors are rectangular. Currently, decoupling capacitors are front-end-of-line (FEOL) only devices and are normally placed in designated chip area during an early stage of chip design. One problem with this approach, however, is that IC development continues to pursue further miniaturization and higher performance, i.e., faster clock speeds. Higher performance increases the need for decoupling capacitance, hence, increasing the need for larger chip area, which results in the increase in chip cost.
On the other hand, certain portions of an IC chip typically include circuit layout with little or no metal in a specific metal wiring layer. Since these areas have a low density for the metal layer, small bits of unconnected metal (fill) are added to increase the density of that metal in that specific area in an effort to meet manufacturing fabrication requirements for chemical-mechanical polish. These shapes are not connected to anything in the IC, so they serve no functional purpose relative to IC functioning.
In view of the foregoing, there is a need in the art for a solution that provides maximized decoupling capacitance on the ICs.